Browsing by Author "Aslam, Sohaib"

Now showing 1 - 9 of 9
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    Design for prognostics and security in field programmable gate arrays (FPGAs).
    (Cranfield University, 2020-03) Aslam, Sohaib; Jennions, Ian K.; Samie, Mohammad
    There is an evolutionary progression of Field Programmable Gate Arrays (FPGAs) toward more complex and high power density architectures such as Systems-on- Chip (SoC) and Adaptive Compute Acceleration Platforms (ACAP). Primarily, this is attributable to the continual transistor miniaturisation and more innovative and efficient IC manufacturing processes. Concurrently, degradation mechanism of Bias Temperature Instability (BTI) has become more pronounced with respect to its ageing impact. It could weaken the reliability of VLSI devices, FPGAs in particular due to their run-time reconfigurability. At the same time, vulnerability of FPGAs to device-level attacks in the increasing cyber and hardware threat environment is also quadrupling as the susceptible reliability realm opens door for the rogue elements to intervene. Insertion of highly stealthy and malicious circuitry, called hardware Trojans, in FPGAs is one of such malicious interventions. On the one hand where such attacks/interventions adversely affect the security ambit of these devices, they also undermine their reliability substantially. Hitherto, the security and reliability are treated as two separate entities impacting the FPGA health. This has resulted in fragmented solutions that do not reflect the true state of the FPGA operational and functional readiness, thereby making them even more prone to hardware attacks. The recent episodes of Spectre and Meltdown vulnerabilities are some of the key examples. This research addresses these concerns by adopting an integrated approach and investigating the FPGA security and reliability as two inter-dependent entities with an additional dimension of health estimation/ prognostics. The design and implementation of a small footprint frequency and threshold voltage-shift detection sensor, a novel hardware Trojan, and an online transistor dynamic scaling circuitry present a viable FPGA security scheme that helps build a strong microarchitectural level defence against unscrupulous hardware attacks. Augmented with an efficient Kernel-based learning technique for FPGA health estimation/prognostics, the optimal integrated solution proves to be more dependable and trustworthy than the prevalent disjointed approach.
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    Digital twin in aerospace industry: a gentle introduction
    (IEEE, 2021-12-20) Li, Luning; Aslam, Sohaib; Wileman, Andrew; Perinpanayagam, Suresh
    Digital twin (DT), primarily a virtual replica of any conceivable physical entity, is a highly transformative technology with profound implications. Whether it be product development, design optimisation, performance improvement, or predictive maintenance, digital twins are changing the ways work is undertaken in various industries with multifarious business applications. Aerospace industry, including its manufacturing base, is one such keen adopter of digital twins with an unprecedented interest in their bespoke design, development, and implementation across wider operations and critical functions. This, however, comes with some misconceptions about the digital twin technology and lack of understanding with respect to its optimal implementation. For instance, equating a digital twin to an intelligent model while ignoring the essential components of data acquisition and visualisation, misleads the creators into building digital shadow or digital models, instead of the actual digital twin. This paper unfolds such intricacies of digital twin technology for the aerospace community in particular and others in general so as to remove the fallacies that affect their effective realisation for safety-critical systems. It comprises a comprehensive survey of digital twins and their constituent elements. Elaborating their characteristic state-of-the-art composition along with corresponding limitations, three dimensions of the future digital twins for the aerospace sector, termed as aero-Digital Twins (aero-DTs), are proposed as an outcome of this survey. These include the interactive, standardisation, and cognitive dimensions of digital twins, which if leveraged diligently could help the aero-DT research and development community quadruple the efficiency of existing and future aerospace systems as well as their associated processes.
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    Enhancing the security of unmanned aerial systems using digital-twin technology and intrusion detection
    (IEEE, 2021-11-15) Fraser, Benjamin; Al-Rubaye, Saba; Aslam, Sohaib; Tsourdos, Antonios
    In this paper the general susceptibilities of Unmanned Aerial Vehicles (UAVs) against modern-cyber threats are explored and potential solutions proposed. This is achieved by applying digital-twin architectures and data-driven methods to UAVs to facilitate identification of real-time intrusions and anomalies. These concepts are validated by performing novelty detection on open access UAV flight data with GPS spoofing attacks, which represents a typical system use-case. Multiple machine learning models are trained to demonstrate the feasibility of detecting modern cyber-intrusions and anomalies using the digital-twin architecture. This includes both classical and deep learning techniques to help identify the most suitable model types for the proposed design. The overall results are positive and help highlight the potential of digital-twin architectures for the UAV contexts.
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    Evaluation of CAN bus security challenges
    (MDPI, 2020-04-21) Bozdal, Mehmet; Samie, Mohammad; Aslam, Sohaib; Jennions, Ian
    The automobile industry no longer relies on pure mechanical systems; instead, it benefits from many smart features based on advanced embedded electronics. Although the rise in electronics and connectivity has improved comfort, functionality, and safe driving, it has also created new attack surfaces to penetrate the in-vehicle communication network, which was initially designed as a close loop system. For such applications, the Controller Area Network (CAN) is the most-widely used communication protocol, which still suffers from various security issues because of the lack of encryption and authentication. As a result, any malicious/hijacked node can cause catastrophic accidents and financial loss. This paper analyses the CAN bus comprehensively to provide an outlook on security concerns. It also presents the security vulnerabilities of the CAN and a state-of-the-art attack surface with cases of implemented attack scenarios and goes through different solutions that assist in attack prevention, mainly based on an intrusion detection system (IDS)
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    Hardware trojans and smart manufacturing – a hardware security perspective
    (IOS Press, 2018-12-01) Aslam, Sohaib; Samie, Mohammad; Jennions, Ian K.
    Integrated Circuits (ICs) are the cardinal elements of modern electrical, electronic and electro-mechanical systems. Amid global outsourcing of ICs' design and fabrication and their growing applications in smart manufacturing or Industrie 4.0, various hardware security threats and issues of trust have also emerged. IC piracy, counterfeiting, and hardware Trojans (HTs) are some of the key hardware threats that merit the attention of manufacturing community. It is worth noting that the lower abstraction levels (ICs) are falsely assumed to operate securely. The proposition, therefore, is that if an operating system (higher abstraction level) is considered to be secure while operating on a compromised IC (lower abstraction level), would it be prudent to regard this implementation as secure? The purpose of this paper is to highlight IC level threats with an emphasis on hardware Trojans that pose a significant threat to smart manufacturing environment in the wake of Industrial Internet of Things (IIoT).
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    Ingress of threshold voltage-triggered hardware trojan in the modern FPGA fabric–detection methodology and mitigation
    (IEEE, 2020-02-11) Aslam, Sohaib; Jennions, Ian K.; Samie, Mohammad; Perinpanayagam, Suresh; Fang, Yisen
    The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship’s integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation.
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    Physics of failure (PoF) based lifetime prediction of power electronics at the printed circuit board level
    (MDPI, 2021-03-17) Wileman, Andrew; Perinpanayagam, Suresh; Aslam, Sohaib
    This paper presents the use of physics of failure (PoF) methodology to infer fast and accurate lifetime predictions for power electronics at the printed circuit board (PCB) level in early design stages. It is shown that the ability to accurately model silicon–metal layers, semiconductor packaging, printed circuit boards (PCBs), and assemblies allows, for instance, the prediction of solder fatigue failure due to thermal, mechanical, and manufacturing conditions. The technique allows a life-cycle prognosis of the PCB, taking into account the environmental stresses it will encounter during the period of operation. Primarily, it involves converting an electronic computer aided design (eCAD) circuit layout into computational fluid dynamic (CFD) and finite element analysis (FEA) models with accurate geometries. From this, stressors, such as thermal cycling, mechanical shock, natural frequency, and harmonic and random vibrations, are applied to understand PCB degradation, and semiconductor and capacitor wear, and accordingly provide a method for high-fidelity power PCB modelling, which can be subsequently used to facilitate virtual testing and digital twinning for aircraft systems and sub-systems
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    Qualitative validation approach using digital model for the health management of electromechanical actuators
    (MDPI, 2020-11-04) Garza, Pablo; Perinpanayagam, Suresh; Aslam, Sohaib; Wileman, Andrew
    An efficient and all-inclusive health management encompassing condition-based maintenance (CBM) environment plays a pivotal role in enhancing the useful life of mission-critical systems. Leveraging high fidelity digital modelling and simulation, scalable to digital twin (DT) representation, quadruples their performance prediction and health management regime. The work presented in this paper does exactly the same for an electric braking system (EBS) of a more-electric aircraft (MEA) by developing a highly representative digital model of its electro-mechanical actuator (EMA) and integrating it with the digital model of anti-skid braking system (ABS). We have shown how, when supported with more-realistic simulation and the application of a qualitative validation approach, various fault modes (such as open circuit, circuit intermittence, and jamming) are implemented in an EMA digital model, followed by their impact assessment. Substantial performance degradation of an electric braking system is observed along with associated hazards as different fault mode scenarios are introduced into the model. With the subsequent qualitative validation of an EMA digital model, a complete performance as well as reliability profile of an EMA can be built to enable its wider deployment and safe integration with a larger number of aircraft systems to achieve environmentally friendly objectives of the aircraft industry. Most significantly, the qualitative validation provides an efficient method of identifying various fault modes in an EMA through rapid monitoring of associated sensor signals and their comparative analysis. It is envisaged that when applied as an add-on in digital twin environment, it would help enhance its CBM capability and improve the overall health management regime of electric braking systems in more-electric aircraft
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    A road map for reliable power electronics for more electric aircraft
    (Elsevier, 2021-06-16) Wileman, A. J.; Aslam, Sohaib; Perinpanayagam, Suresh
    The gradual evolution from hydro-pneumatic to electrical disposition of power in aircraft has placed stringent requirements on the reliability of power electronic components in current and future aerospace applications. This paper examines the prevalent state-of-the-art in power electronics and provides an analytical overview of power electronics in More Electric Aircraft (MEA) vis-à-vis the generation and distribution of power within these aircraft. The types of power devices currently employed for multiple conversion topologies are analysed and weighed according to their respective reliability characteristics. Beginning with an in-depth review of failure modes in the currently available devices, the paper highlights the salient emerging state-of-the-art Wide Band Gap (WBG) technologies such as Gallium Nitride (GaN) and Silicon Carbide (SiC) and draws an extensive comparison with their Silicon counterparts. A comprehensive examination of techniques employed for the estimation of the reliability of WBG power devices has revealed a number of areas that merit due consideration. For instance, the physics-based models that have been developed to assess the operational lifetime of silicon-based devices for given failure modes require revamping in light of the new materials and the unique electrical and physical characteristics the WBG devices possess. Similarly, the condition monitoring techniques, with respect to the primary and secondary parameters, require further investigation to determine highly representative feature vectors that best describe the degradation within these devices. More significantly, optimisation of the proposed techniques for the health assessment of these devices needs to be pursued through the optimal use of vital parameters. Keeping these critical findings in perspective, a road map highlighting various avenues for power electronics optimisation in MEA is put forth to apprise the aerospace fraternity of its growing significance.